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Clock Manager (CM) for FPGA
- Project name
- - Clock Manager (CM) for FPGA
- Project objective
- - To develop an integrated clock manaer (CM) for an FPGA chip in a CMOS technology
- Project Contents & Scope
- - The clock manager (CM) is a necessary part of global clock network in FPGAs. The CM provides advanced clock output to FPGA applications.
- - Primarily, the CM eliminates clock skew by using DLL to improving system performance. The CM can control the phase shift of the input clock to make various phases of output clock. The CM can multiple or divide the frequency of the input clock to synthesize new output clocks. In this research, the CM will be integrated with spread spectrum clock generation (SSCG) function expanding to consumer display application.
- - Moreover, the developed CMs will be integrated directly with the FPGA's low skew global clock distribution network
- Project Result
- Project Term
- Project Sponsor