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차충렬(Choong-Yul Cha)
  • 042-866-6284

Education   

  •  2002~Currently: Ph.D Candidate, ICU, Korea.
  •  2000~2001: M.S, Engineering, ICU, Korea.
  •  1991~1994: B.S, Engineering, ICU,Korea.

    • Experience

    •  Lieutenant, Korean Air Force[1997.02~2000.01]
    •  Design engineer, Fiber Optic/RF/Linear ICs, GAINTECH.Inc[2002.01~2003.12]
       

    Research area 

    • Researcg & Interest
         - Analog/RF ICs: LNA, Mixer, VCO,VGA, Filter, etc.
         - One-Chip Radio Transceiver and Wireless System
         - High Speed Fiber Optic ICs: LDD, AGC-TIA, Limiting Amplifier
         - High Speed Mixed Signal ICs: Pll, CDR, etc.
         - Power Management ICs

    Design Experience

    •  
      Radio Frequency ICs
      LNA for Bluetooth and Wireless LAN(5GHz)
      - Period:Yr.2000~Yr.2001
      - Technology: 0.35 m CMOS
      - Design Concept:High Gain/Low Power Consumption, Substrate Optimisation
       
      Single Chio Double Conversion Tuner for Cable Modem Application
      - Period: Yr.2000~ Yr.2001
      - Technology: 0.5 m BiCMOS, ft=15GHz
      - Designed Buliding Blocks:
         +Up Conversion VCO, Active Balun and LO Driver Amp
         +Down Concersion VCO and LO Buffer Amp
         +Down Conversion Image Rejection Mixer
         +Down Conversion IF Amplifier
      - Design Target: Prototype IC Debelopment With Samsung Electro-Mechanics
       
      Fully Integrated Complimentary Colpitts VCO for Wireless LAN(5GHz)
      - Period: Yr.2002
      - Technology: 0.35 m CMOS
      - Design Concept: New VCO Topology, Phase Noise Analysis and Optimization
      - Patented: 2003.09.12
       
      Dual-Band Vco Modules for mobile communication
      - Period:Yr.2003
      - Technology:0.35 m CMOS
      - Application: GSM,DCS, CDMA, PCS, K-PCS, GPS, WCDMA
      - Design Target: Low Profile and Low Cost
    •  
      Fiber Optic ICs
      AGC-TIAs for OC-3(155Mbps), OC-48(2.5Gbps) and Ethernet(1.25Gbps)
      - Period:Yr.2002~2003
      - Technology: 0.8 m BiCMOS and 0.8 m SiGe Bipolar
      - Design Target:Development of Commercial Product
      - Engaged in the design of Limiting Amplifier and LD driver ICs
       
      10Gbit/s CMOS Differential TIA
      - Period: Yr.2003
      - Technology: 0.18 m RF CMOS
      - Edsign Concept: Active Peaking Techique

    Affiliation

    •  Affiliation: Information and Communications University