Low Supply and Low Jitter PLL Based Frequency Synthesizer Design

• Project name
  • - Low Supply and Low Jitter PLL Based Frequency Synthesizer Design
• Project objective
  • - Low Supply and Low Jitter PLL Based Frequency Synthesizer Design in Deep Submicron(45nm) CMOS Process
• Project Contents & Scope
  • - Projec Contets :
    • - Low Supply/Low jitter/Wide tuning range analog CP Design
    • - Low Supplu/ Low phase noise/ wide tuning range VCO Design
    • - Spur rejection/reduction mechanism Design
  • - Process&Specification :
    • - 65/45nm CMOS
    • - Supply Voltage< 1V
    • - Integrated RMS Jitter < 1.5ps@880MHz
    • - SFDR >50dB
• Project Result
  • 
• Publications
• Project Term
  • - 2008.04~2010.01
• Project Sponsor
  • - ETRI