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- + Development of the Wireless Power Converter System for Mobile Handset
- + 1nJ/bit ULP(Ultra Low Power) 통신 핵심기술 개발
- + Stop Lamp Switch Driver IC
- + UHF band RFID system
- + 1-D Pulsed TOF LADAR Receiver for military application
- + Unipolar Impulse Radar IP Development
- + 평판 디스플레이용 반도체 설계 인력 양성 사업
- + Predictable SoC architecture & modeling
- + 4세대 이동통신용 LNA 설계
- + Low Supply and Low Jitter PLL Based Frequency Synthesizer Design
- + Development of digital-RF IC for ATCS compatible tuner
- + Impulse UWB Rader IC Design
- + Cordless mouse RF transceiver IP Development
- + Development of tuner RFIC for digital TV Applications
- + Spread Spectrum Clock Generator for TCONT application
- + CMOS FM Receiver Development
- + Clock Manager (CM) for FPGA
- + IR-UWB transceiver Design
- + High input-impedance voice ADC for digital microphone
- + IT-SOC
1nJ/bit ULP(Ultra Low Power) 통신 핵심기술 개발
- Project name
- - 1nJ/bit ULP(Ultra Low Power) 통신 핵심기술 개발
Project objective - - Development ultra-low power (ULP) receiver
- Project Contents & Scope
- - Project 과제 필요성
- Project 주요 contents
- - Ultra-low power receiver architecture with multi-channel operation
- - Ultra-low power LNA
- - Ultra-low power VCO
- - Ultra-low power periodic ON/OFF PLL
- 1차년도 목표
- - Power consumption: 150uW
- - Receiver sensitivity: -70dBm
- - Data-rate: 1Mbps
- - Frequency: 2.36~2.5GHz
- - Channel BW/Spacing: 1.5/5MHz
- - Modulation: OOK
- 최종 개발 목표
- - Power consumption: 100uW (Rx excluding PLL)
- - Receiver sensitivity: -85dBm
- Technical breakthrough
- Project Result
- Project Term
- - 2011.03 ~ 2014.03 (3 years)
- Project Sponsor
- - 방송통신위원회 방송통신인프라원천기술개발사업 (주관기관 : 삼성전자)
